Simplified error-control decoder



De 7, 1965 c. H. BURTON ETAL 3,222,644

SIMPLIFIED ERROR-CONTROL DECODER 4 Sheets-Sheet 1 Filed July 26, 1962mm2@ ZOTPSZmOuZH QmQOQmQ mi, d mmh t r u c w @BHW tHM. A n HE .W e am eV m a Zh I l c Oil Ud CM ,D .zum f .OZ\wm. \N mw m EE \\m. oomooozm oDec. 7, 1965 c. H. BURTON ETAL 3,222,644

SIMPLIFIED ERROR-CONTROL DECODER 4 Sheets-Sheet 2 Filed July 26, 1962Dec. 7, 1965 Filed July 26, 1962 C. H. BURTON ETAL S IMPLIFIEDERROR-CONTROL DECODER 4 Sheets-Sheet Coleman H. Burton,

Michael E. Mitchell,

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Dec. 7, 1965 c. H. BURTON ETAL 3,222,544

SIMPLIFIED ERROR-CONTROL DECODER Filed July 26, 1962 4 Sheets-Sheet 4-l-REF.

REF -BlAS Vlg. 5B lieu/xsl |REf-Tl Coleman l-LBur'toh, Michael E.Mitchell,

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United States Patent "a 3,222,644 SIMPLIFIED ERRUR-CNTRL DECDER ColemanH. Burton `and Michael E. Mitchell, Ithaca, NX., assignors to GeneralElectric Company, a New York corporation Filed .lilly 26, 1962, Ser. No.212,746 Claims. (Cl. S40-145.1)

The invention is directed to error correcting apparatus for digital dataprocessing systems. The apparatus is of the class which operates upon(and generates) code words (or sequences of n digits) which arecharacterized by consisting of k information `digits plus n-k redundantdigits whereby errors can be corrected by means of the redundant digits.The apparatus will not correct all possiblecombinations of errors, butit can correct up to a given number with certainly and :some additionalerrors under special circumstances and perform other related functionssuch as monitoring the number and rate of error corrections. Theinvention results in great simpliication of apparatus with certaincodes.

For many years, a great deal of successful work on the theory of error`correcting codes has been carried out. There have also been substantial`developments in apparatus for the encoding of many kinds of errorcorrecting codes. However, there has been a distinct lack of success inproviding corresponding decoding apparatus of practical simplicity.Infact, prior decoding systems are frequently characterized by marginalincreases of overall reliability because the mass of additional decodingapparatus tends to introduce as many errors as it corrects.

In respect to some considerations, the use of error correction codes isthat by transmitting information over a longer time period at the samepower, more energy is made available and thus greater signal-to-noiseratio is obtainable. However, it is necessary to provide the addedsignal energy in such a manner that there can be eiiicientdiscrimination of the information signal. The relations involved can `beapproached with various kinds of analysis and a very large body ofcomplex theory exists.

For the purposes of explanation, a representative code will beconsidered here in the specification. This code is known as the (l5, l)code. It is characterized by consisting of 11:15 binary characters orbits of which k:,7 are `the information bits and n-kz- S bits areredundant bits which provide an error correcting capability of at least2 errors in each code word.

If one has 7 information bits, there are 27 possible binary combinationsor words and there are 215 possible combinations for a 15 bit sequence.lt is evident that the additional redundant digits can provide a greatdeal of correction data to determine where errors are. In fact, it hasbeen determined that theseven information bits can `be encoded so thatall possible correct wond combinations will differ from each other in atleast live places of their `fifteen bit code word. As a result, if areceived code word has two errors or less, and it is compared withthe`2'I correct words, the closest code word will be the correct onebecause all other possible correct code words will `differ in at leastthreeplaces.

`techniques for extracting signal from noise plus signal.

3,222,644 Patented Dec. 7, 1965 ICC The several techniques arecharacterized by the fact that the decoding procedure is a bit-by-bitoperation in which the following two-step rountine is iterated: First, acalculation of the several estimator values for the ith transmitted codedigit (or for mod 2 sums of selected code digits) wherein each estimatoris based on, or may actually consist of, a mod 2 sum of code digitsidentically equal to the estimated code digit (or mod 2 sum of codedigits) when no errors are present. Second, a combination of the severalestimator values for each estimated quantity into a nal estimate,wherein the final estimate `for the (i-{-l)th quantity diiiers Vfromthat for the z'th only by a unit cyclic permutation of the digits(modulo the code length n) appearing as arguments in the estimators.

Regarding the second step, the combining operation for binary decodingwith an odd number of estimators is merely the majority decisionoperation. Binary decoding with an even number of estimators isaccomplished by deciding according to an arbitrary rule in case `of atie (and by majority decision otherwise). If a particular estimator isinherently more reliable for the expected kind of error-producingmechanism, it should obviously be used to break ties. (In most cases,the single-digit estimator is more reliable.) In some cases of equalestimator reliability (or credibility), the best arbitrary rule forbreaking ties may be pseudorandom choice, or even a truly random choice.

The most significant feature of the invented decoding techniques is notthe variety of detailed differences between specific decoding procedures(and `their implementation), but instead consists of the fact that eachdecoding procedure `within the scope of the defined invention employs adecoding function which is independent of the particular quantity beingdecoded. Thus, the quantity which is decode-d according to the abovesteps always consists of code digits. In spite of the superficialdifferences, the inherent reason for the simplicity with which theseveral invented decoding techniques can be implemented is based on thenearly complete exploitation of the cyclic properties of the codesemployed.

Accordingly, it is an object of this invention to provide a simplifiedplural error correction decoder which does not require the complexapparatus for an intermediate series of logic operations on the complete`Word before the final decoding of any digits in the code word.

It is a further object of the invention to provide a simplified pluralerror correction decoder which does not require a plurality of storagedevices for intermediate logic evaluator operations.

It is another object of this invention to provide a decoder whichdoesnot require the decoding of the complete code word to decode theinformation digits.

These and other objects and features of the present invention willbecome apparent from the accompanying detailed description and drawingsin which:

FIGURE l is a block diagram of a one `way digital communication systemillustrating binary encoding and decoding;

FIGURE 2 is a block diagram of an encoder and decoder for a (15, 7)code;

FIGURE 3 is a schematic diagram of one `stage of a shift registersuitable for use in the FIGURE 2 encoder or decoder;

FIGURE 4 is a schematic diagram of a two-input modulo 2 adder for theestimator logic circuits in the FIGURE 2 decoder; and

FGURES 5A and 5B are `schematic diagrams of a majority logic circuit forthe FIGURE 2 decoder.

Referring now to the drawings, FIGURE 1 is a block diagram of arepresentative one-way digitalcommunications system. A data source 2supplies informationin the form of digital signals such as code wordswhich it is desired to transmit to a remote data utilization device 9.The code word illustrated is a three digit message, a1, a2, a3, shown as101, which is applied to an encoder in a serial or parallel operation.The output of the encoder is a series of bits (al, a2, a7) in which thelast four are redundant bits generated by the encoder. These redundantbits are generated as predetermined logic functions of the informationbits so that the bits are logic functions of both redundant andinformation bits. The code word is then transmitted by transmitter l bysequential bits in accordance with cotnrol pulses from a conventionalsynch generator 5. As illustrated, the message received by receiver 6has an error in the third place b3. When the complete message isreceived, it has been stored in the decoder 8 under control of synchgenerator 7 by conventional digital data transmission techniques. Thedecoder 8 then operates upon the received word, including the erroneousthird bit b3, and by sensing the redundant bits (together with theinformation bits), determines the correct values for b1, b2, b3 whichare then applied to the utilization device 9.

The apparatus of FIGURE 1 is characterized by the addition of an encoderand a decoder without modification of the `original system components.The result is that system performance can be vastly improved withoutredesign of the system. With the novel decoder disclosed herein, theinformation is read out of the decoder during k operations followingreception of the code word. This is permitted by minimizing the numberof the sequential bit decoding operations to the number of informationbits in the encoded word.

FIGURE 2 is a block diagram illustrating the major components of theinvention aranged for encoding and decoding a (15,7) code. The encoder 3is of a conventional design. Itis comprised of a seven stage shiftregister 12 which is adapted to receive an information word of sevenbits in parallel by suitable gating means. The information word isencoded by simultaneously generating redundant bits and reading out thecode wbrd bits during cyclic serial operations. Each clock pulse causesthe bit signals in each stage to shift to the right to the next stage.The signals from the last stage are the output bit signals of theencoder 3. During each shift operation, a redundant bit signal isgenerated by the modulo 2 adder and is entered into the first stage ofthe shift register l2. The mod 2 adder generates each redundant bit inaccordance with the modulo sum of the three bits in the stages where a1,a5 and a7 were originally entered. The mod 2 adder is conveniently apair of two input mod 2 adders in series in which a1 and a5 are appliedto the first and the output of the first and a7 are applied to thesecond. An appropriate mod l2 adder will be described hereinafter, butit can take any form such as a simplified half adder wherein the sumsignal is the output. (The output of each modulo 2 adder in operation isthe binary sum casting out all carries.)

The result is that after clock pulses, a code word will be generated inwhich the Iirst seven bits are the same as the information bits and theeight redundant bits are as follows:

lhamflias Because of their cyclic characteristic, the redundant bits areserially generated as the code word bits are shifted out of the shiftregister 12.

The decoder 8 in FIGURE 2 includes three major functional units: a15-stage shift register 16, single-digit cyclic estimator logic circuits22-25, and a majority logic circuit 30. A mode switch 15 selects eithera load mode or a decode mode by switching the serial input of the shiftregister 16 either to the incoming code word or to a feedback connectionfor entering decoded bit signals sequentially. The cyclic estimatorlogic circuits 22-25 are each connected to three stages of the shiftregister 16 in accordance with an independent logic equation. Each ofthese cyclic estimator logic circuits are of the same type as the mod 2adder 13 in encoder 3. Because of the relations of the redundant bits tothe information bits, the information bits can be estimated from thecode bits in several ways which rely on independent selections of thecode word bits. In the absence of any errors, the outputs of all thecyclic estimator logic circuits are the same. However, in the event ofone or two errors, the majority logic circuit 30, since it is arrangedto receive the outputs of all cyclic estimator logic circuits, providesan output signal in accordance with the majority `of the estimators. Inthis embodiment, there are four mod 2 estimators and a fth estimate ofal is provided for the majority logic circuit 30 directly, by the laststage of the shift register which contains b1. This logic operation isused once for each digit, and will always produce a correct majoritylogic output if there are two err-ors or less in the received code wordbecause three of the estimates must be correct.

The sequence of the decoding operations in the decode mode is describedas follows. First assume that bj is the binary quantized received valueof the code digit transmitted as aj, for j: 1, 2, 15; and that Rj is thebinary value of the contents of the jth stage of the 15-stage shiftregister where jzl, 2, 15. Then the procedure is:

(1) Compute the estimator logic functions where (B is the symbol formodulo 2 addition (2) Compute the majority decision estimate B1=MajorityF1, F2, F3, F4, F5

(3) Feed B1 (the estimate of the binary content of the terminal stage,R1) back to the stage of entry, R15, while shifting the contents of all15 stages to the right by one unit.

(4) Repeat steps 1-3 for a total of seven complete cycles, then STOP.

(5) Read out the corrected information bits from Stages R15, R14, R9.

Note that the iirst time step 1 is executed, the binary digit in the jthstage has the value Rjzbj, where bj is the binary quantized receivedvalue of the digit transmitted as aj for jzl, 2, 15. However, the secondtime that step l is executed, the binary content of the ith stage isRJ-:bJ-H. The process, of course continues. The important feature hereis that the decoding procedure itself is independent of the contents ofthe shift register. In fact, the process can be allowed to continueindefinitely; and if, at any step, two or fewer errors exist, they willbe corrected, and from that point on a completely correct c-ode wordwill circulate. The invariance of this procedure to the shift-registercontents is clearly advantageous from operational and implementationstandpoints.

Two alternative information readout modes are possible:

(l) Serial readout of the sequence of estimated information bits au, a1,a6 in the time sequence with which they are decoded.

(2) Parallel readout of these bits as a single word 15 a7 from thecontents of register stages 9 through The particular decoding procedureindicated in steps 1 through 4 is described as bit-by-bit single-stagedecoding with feedback, which is abbreviated to merely stepby-stepsingle-stage decoding for either of these information readout modes.

Instead of feedback of corrected digits, suppose that `the uncorrecteddigits were merely recirculated. Thedecoding procedure would be calledbit-by-bit as before, but could no longer allow parallel readout(without adding external storage), nor could it be legitimately calledstep-by-step. This is because of the `prevailing use of the termstep-by-step to mean a succession of decoding steps toward the correctmessage. This criterion is indeed satisfied with the type ofsingle-stage decoding procedure having feedback illustrated in FIGURE 2.In this particular example, a step is defined as the correction andfeedback to the shift register of a digit which was received in error.Each such operation may reduce the Hamming distance between the AWordstored in the register andthe correct word by one unit, which is calleda stepf It is evident that the decoder arrangement of FIGURE 2 isadaptable to various other codes. Examples of such codes are: (21, 1l),(73, 45) and (Zm-L m). The requirements of the codes which are ideallysuited for this type of decoder are involved. The practical limitationis the ability to form a set of estimator logic equations which areindependent (have no common terms) and are of sufficient number so thatthe theoretical maximum number of errors can be corrected. In addition,of course, the code must be a cyclic, binary group code so that therecursion relationship enables utilization of the same circuitry forsuccessive bits.

The above codes such as (73, 45 have been known as cyclic binary groupcodes and from their known properties, their estimator logic equationscan be determined. For the (73, 45) code, the equations as formed for a1are as follows:

a1=llsan@azsdazlaollavda-iadllto tl1=an691123@aztllzsllasanludanllt='11569111569020631121EBaazGBuaGamGae lli=tlzElBadlliaawlanlasoandaeoIt is to be understood that there are many variations in the dataprocessing systems incorporating the disclosed decoder. The radiotransmission system illustrated in FIGURE 1 is only representative. Thedata link transmission systems between the encoder and decoder canincorporate different combinations and permutations of parallel andserial data transmissions, from physical movement f punched cards tointricate systems.

The implementation of the FIGURE 2 decoder may be carried out withconventional components. For example, the shift registers 12 and 16 canbe implemented by a series of standard flip-ops such as shown in FIG-URE 3. Each Hip-flop Rn, is a single stage in the shift register and isinterconnected with the adjoining stages RM1 and Rn 1. In the preferredembodiment of the system, a l bit signal is in the form of a positivevoltage and a "0 bit is in the form of a zero voltage level. Therefore,the n-p-n transistors 41 and 42 are interconnected so that when theflip-Hop is set, the right-hand transistor 42 is conducting and theleft-hand transistor 41 is olf. Accordingly, a positive voltage appearsat the output terminal 45 as F and a zero voltage appears at thecomplementary output terminal 46 as When the negative going clock pulseis applied to the base of each transistor, the conducting transistor iscut olf. Upon removal of the clock pulse, the Hip-flop circuit assumes aset or reset state in accordance with the last state of the precedingstage. That is, the output signals of stage RM1 are connected to `inputterminals 43 and 44 so that S :FMI (before the shift) and R11-FMD It isto be understood that in decoders having an even number of estimators,the majority decision would include `tie-breaking functions'such asselection of the bj value to be decoded.

A suitable component for the mod 2 adder is shown in FIGURE 4. Theillustrated circuit is a `two-input mod 2 adder in itself and has itsoutput coupled to one of the inputs of an identical two-input mod 2adder. The n-p-n transistors 51 and 52 operate to produce a positivevoltage at the output terminal 57 in accordance with an exclusive orlogic function. If either input, A at input terminal 53 or B and E atinput terminals 54 and 54', is a l the output atterminal 57 is apositive voltage and if the inputs are both either ls or 0s, the outputsignal is a zero voltage. This is because the transistor 52 isconducting only if E and A provide positive voltages or if B provides apositive voltage while A provides a zero voltage.

FIGURES 5A and 5B illustrate a preferred majority logic circuit. Thiscircuit receives the output of all the estimator logic circuits 22-25 atinput terminals 61. Since it combines all of the input signals into ananalog signal, it is fundamental that these signals be accurate`voltages so that a correct comparison is made. Accordingly, clampingcircuits 62 are provided to regulate the cornparison voltages. Eachclamping circuit includes a Zener diode 63 which produces a voltagereference for a standard transistor clamping circuit. Because of thebalanced reference and bias sources, the voltage at one of the clamp-.ing circuit output terminals 64 and 64 is negative or positive and theother is zero. These carefully referenced signals (negative for lestimation and positive for a zero estimation) are then applied to a setof precision `summing resistors whichV sum the signals. The output ofthe summing network can assume any one of six levels. Accordingly, an-output circuit consisting -of three transistors 67, 68 and 69 isprovided so that the output signal of the majority logic circuit atterminal 70 assumes either a zero value for a 0 bit or a positive signalvalue for a l bit of the decoder circuits. The transistors 68 and 69therefore produce either a fixed positive voltage or a zero voltagedepending upon whether transistor 67 is turned on or olf by the majoritysum of the estimator signals. The output voltage remains constantregardless of variations in the transistor 67 current.

The construction of the decoder can be carried out with other standardcomponents. For example, binary scaler counters can be used as themodulo 2 adders and other shift registers such as magnetic core shiftregisters can be employed. The control circuit 29 in the FIGURE 2 systemprovides the normal data processing control functions. These -functionsinclude providing clock pulses to the various components and prtovidingcommand signals to stop decoding functions after the information bitsare decoded and to readout the decoded bits.

While particular embodiments 'of the invention have been shown anddescribed herein, it is not intended that the invention be limited tosuch disclosure, but that changes and modifications can be made andincorporated within the scope of the claims.

1. In data processing apparatus that processes code words having nbinary digit signals in n respective positions in the word, of which ksignals represent information bits, a decoder comprising:

(a) A register adapted to receive the code word signals in such a mannerthat the bits of the code word signals are entered into positions of theregister corresponding to their position in the code word;

(b) cyclic estimation logic circuits which operate as a function of thereceived bits in said register in a manner to Iprovide the requirednumber of estimate signals by independent value estimations of thecorrect value of the received bit in a specific position of theregister;

(c) a decision logic circuit responsive to the estimate signals toprovide decoded output bit signal in accordance with the majority of theestimate signals; and

(d) control circuitry to cyclically shift the bit signals in saidregister for k bit decoding operations, to initiate a bit decodingoperation after each shift,

' and to terminate word decoding operations after k bit decodingoperations.

2. In data processing apparatus that processes code words having nbinary digit signals in n respective positions in the w-ord, of which ksignals represent information bits, a multiple error :correction decodercomprising:

(a) a shift register adapted to receive the code word signals in such amanner that the bits of the code word signals are entered into positionsof the shift register corresponding to their position in the code word;

(b) cyclic estimation logis circuits which operate as a function of thereceived bits in said shift register mate signa-ls by independent valueestimations of the correct value of .the received bi-t in a specifiedposition of the shift register;

(c) a majority logic circuit responsive to the estimate signals toprovide a decoded output bit signal in accordance with the majority ofthe estimate signals;

(d) feedback means to enter the decoded bit signals into said shiftregister; and

(e) control circuitry to cyclically shift the bit signals in saidregisters lfor k bit decoding operations, to initiate a bit decodingoperation after each shift, and to terminate word decoding operationsafter k bit decoding operations.

3. The multiple error correction decoder of claim 2 for decoding a (l5,7) code wherein:

(f) said cyclic estimation logic circuits incldue a plurality of 4modulo2 adders which each provide an estimate of a bit being decoded inaccordance with the following estimator equations,

OTHER REFERENCES April 24, 1959, Fire, A Class ofMultiple-Error-Correcting Binary Codes for Non-Independent Errors,Stanford Electronics Laboratories, Technical Report No. 55.

Oct. 1958, Green et al., An Error Correcting Encoder and Decoder of HighEciency, Proceedings of the IRE.

ROBERT C. BAILEY, Primary Examiner.

MALCOLM A. MORRISON, Examiner.

UNITED STATES PATENT OFFICE CERTIFICATE 0F CORRECTION Patent No.3,222,644 December 7, 1965 Coleman H. Burton et al.

It is hereby certified that error appears in the above numbered patentrequiring correction and that the said Letters Patent should read ascorrected below.

Column 4 line 36 for "F2=R5@R7=R8" read F2=R50R7R8 column 5, line 50,for "a5=" read al= column 7,

line 27, after "register" insert in a manner to provide the requirednumber of estiline 37, for "registers" read register line 43, for"incldue" read include column 8, lines 2 to 5 should appear as shownbelow instead 3 of as in the patent:

same column 8, line 20, strike out plural".

Signed and sealed this 3rd day of January 1967.

(SEAL) Attest: v

ERNEST W. SWIDER EDWARD J. BRENNER Attesting Officer Commissioner ofPatents

1. IN DATA PROCESSING APPARATUS THAT PROCESSES CODE WORDS HAVING NBINARY DIGIT SIGNALS IN N RESPECTIVE POSITIONS IN THE WORD, OF WHICH KSIGNALS REPRESENT INFORMATION BITS, A DECODER COMPRISING: (A) A REGISTERADAPTED TO RECEIVE THE CODE WORD SIGNALS IN SUCH A MANNER THAT THE BITSOF THE CODE WORD SIGNALS ARE ENTERED INTO POSITIONS OF THE REGISTERCORRESPONDING TO THEIR POSITION IN THE CODE WORD; (B) CYCLIC ESTIMATIIONLOGIC CIRCUITS WHICH OPERATE AS A FUNCTION OF THE RECEIVED BITS IN SAIDREGISTER IN A MANNER TO PROVIDE THE REQUIRED NUMBER OF ESTIMATE SIGNALSBY INDEPENDENT VALUE ESTIMATES OF THE CORRERECT VALUE OF THE RECEIVEDBIT IN A SPECIFIC POSITION OF THE REGISTER; (C) A DECISION LOGIC CIRCUITRESPONSIVE TO THE ESTIMATE SIGNALS TO PROVIDE DECODED OUTPUT BIT SIGNALIN ACCORDANCE WITH THE MAJORITY OF THE ESTIMATE SIGNALS; AND (D) CONTROLCIRCUITRY TO CYCLICALLY SHIFT THE BIT SIGNALS IN SAID REGISTER FOR K BITDECODING OPERATIONS, TO INITIATE A BIT DECODING OPERATIION AFTER EACHSHIFT, AND TO TERMINATE WORD DECODING OPERATIONS AFTER K BIT DECODINGOPERATIONS.